|alexis e690eccaf2||1 year ago|
|atf1502-jtag-adapter||1 year ago|
|gen||1 year ago|
|misc||1 year ago|
|.gitignore||1 year ago|
|README.md||1 year ago|
ATF150x JTAG adapter
This board is a plug-in adapter to program ATF150x CPLDs on a J-Link. It supports both 5V and 3.3V variants, and provides testpoints to inject 12V to unlock a locked device.
For parts, see the schematic fields. "BOM" numbers are references to my internal stock keeping system, but you should be able to find equivalents easily. I may have spare PCBs on hand too, just ask.
Powering the board
This board is meant to be powered directly by the J-Link. To enable power
delivery, use the command
power on from the control utility. If you always
want this, try
power on perm. Note that power is supplied out a separate pin
that is normally not used, so this is generally safe to keep enabled.
Programming the chips
The process needed to program these is pretty unobvious. Here's what I do:
- Create a logic file in WinCUPL. You should get a .JED output.
- Use ATMISP7 (same link) to translate this to a .svf
- Create a new one-device chain
- Set the device name appropriately
- Select "Program/Verify" as the JTAG instruction
- Select your .JED file as the "JEDEC File"
- Choose "Write SVF file"
- Program using openocd:
openocd -f /usr/share/openocd/scripts/interface/jlink.cfg \ -c "adapter speed 400" \ -c "transport select jtag" \ -c "jtag newtap ATF1502AS tap -irlen 3 -expected-id 0x0150203f" \ -c init \ -c "svf FILENAME.svf" \ -c "sleep 200" \ -c shutdown
Note that the chip name and ID in this command don't actually need to match (they may be able to be removed entirely).
Intellectual property is bullshit. This is everyone's design.
Contact me (issue reports, patches, bare board requests)
Send an email to my username at alexisvl.rocks. I suggest mentioning the project name in the subject line.