Support CH32V30x
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.docker_includes
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.have_docker
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tags
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.cache
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@ -1,3 +1,6 @@
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[submodule "subprojects/ch32v103-meson"]
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path = subprojects/ch32v103-meson
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url = git@gitea.alexisvl.rocks:alexisvl/ch32v103-meson.git
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[submodule "subprojects/ch32v30x"]
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path = subprojects/ch32v30x
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url = git@gitea.alexisvl.rocks:alexisvl/ch32v30x-meson.git
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[submodule "subprojects/ch32v10x"]
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path = subprojects/ch32v10x
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url = git@gitea.alexisvl.rocks:alexisvl/ch32v10x-meson.git
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27
README.md
27
README.md
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@ -1,9 +1,15 @@
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# WCH CH32V103 build template
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# WCH CH32V build template
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This repository is a template for a project built for the WCH CH32V103 RISC-V
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microcontroller, _without_ using the [MounRiver tools](http://mounriver.com/).
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A GCC toolchain is built in a Docker container to make the build simple on all
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decent platforms; I use it on macOS and have tested it on Linux.
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This repository is a template for a project built for the WCH CH32V RISC-V
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microcontroller series, _without_ using the
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[MounRiver tools](http://mounriver.com/). A GCC toolchain is built in a Docker
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container to make the build simple on all decent platforms; I use it on macOS
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and have tested it on Linux.
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## Supported parts
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- CH32V10x family
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- CH32v30x family
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## You will need
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@ -74,22 +80,20 @@ The directory tree contains:
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- `Startup/` — startup/CRT code
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- `mbuild/` — output build directory
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- `src/` — project source code
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- `ch32v10x_it.c` and `.h` — interrupt handlers (this file is not special, you could delete it)
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- `main.c` — contains `main()`
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- `mcu_config.h` — some hardware configuration I factored out of the WCH libs
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- `system_ch32v10x.c` and `.h` — clock/power startup code
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## Making it yours
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- Put code under `src/` (you can start in `main.c` if you like)
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- Edit `meson.build` to list the files that need to be built, and select which peripheral libraries you want
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- Consider changing the project name from `firmware` for more descriptive filenames
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- Make sure to only include either the CH32V10x block or the CH32V30x block
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- Replace this readme with your own
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## Changes I made to the WCH support code
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- Pull user config values out of `system_ch32v10x.c` and `ch32v10x.h` into
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`mcu_config.h`.
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- Pull user config values out of `system_ch32v10x.c` and `ch32v10x.h` and
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define them via meson options.
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## Other useful resources
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@ -98,6 +102,9 @@ here:
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- [CH32V10x datasheet](http://www.wch-ic.com/downloads/CH32V103DS0_PDF.html)
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- [CH32x10x reference manual](http://www.wch-ic.com/downloads/CH32xRM_PDF.html) — beware that this also covers the Cortex-M version
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- [CH32V303/305 datasheet](http://www.wch-ic.com/downloads/CH32V20x_30xDS0_PDF.html)
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- [CH32V307 datasheet](http://www.wch-ic.com/downloads/CH32V307DS0_PDF.html)
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- [CH32x30x reference manual](http://www.wch-ic.com/downloads/CH32FV2x_V3xRM_PDF.html) — beware that this also covers the Cortex-M version
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## Copying and changing
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17
meson.build
17
meson.build
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@ -4,11 +4,19 @@ project(
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default_options: ['optimization=2', 'cpp_std=c++17', 'b_staticpic=false']
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)
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ch32v103_proj = subproject('ch32v103-meson')
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ch32v103_dep = ch32v103_proj.get_variable('ch32v103_dep')
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ch32v103_sys_dep = ch32v103_proj.get_variable('ch32v103_sys_dep')
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## END USER MUST MODIFY: KEEP ONLY THE 10x or 30x BLOCK
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ch32v10x_proj = subproject('ch32v10x')
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ch32v10x_dep = ch32v10x_proj.get_variable('ch32v10x_dep')
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ch32v10x_sys_dep = ch32v10x_proj.get_variable('ch32v10x_sys_dep')
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dependencies = [ch32v10x_dep, ch32v10x_sys_dep]
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linker_script = 'subprojects/ch32v10x/Ld/Link.ld'
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dependencies = [ch32v103_dep, ch32v103_sys_dep]
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## END USER MUST MODIFY: KEEP ONLY THE 10x or 30x BLOCK
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ch32v30x_proj = subproject('ch32v30x', default_options: ['variant=CH32V307'])
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ch32v30x_dep = ch32v30x_proj.get_variable('ch32v30x_dep')
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ch32v30x_sys_dep = ch32v30x_proj.get_variable('ch32v30x_sys_dep')
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dependencies = [ch32v30x_dep, ch32v30x_sys_dep]
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linker_script = 'subprojects/ch32v30x/Ld/Link.ld'
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sources = [
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'src/main.c',
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_incl_dirs = include_directories(includes)
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linker_script = meson.get_external_property('linker_script', '')
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if linker_script != ''
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fn = meson.source_root() / linker_script
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add_project_link_arguments('-T' + fn, language: ['c', 'cpp'])
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@ -3,9 +3,6 @@ arch = 'rv32imac'
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abi = 'ilp32'
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gcc_target = 'riscv32-unknown-elf-'
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[properties]
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linker_script = 'subprojects/ch32v103-meson/Ld/Link.ld'
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[host_machine]
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system = 'baremetal'
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endian = 'little'
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@ -1,14 +0,0 @@
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#include "ch32v10x_it.h"
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__attribute__((interrupt))
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void NMI_Handler(void)
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{
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}
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__attribute__((interrupt))
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void HardFault_Handler(void)
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{
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while(1)
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{
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}
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}
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@ -1,4 +0,0 @@
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#ifndef __CH32V10x_IT_H
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#define __CH32V10x_IT_H
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#endif /* __CH32V10x_IT_H */
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#include <stddef.h>
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#include <inttypes.h>
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#include "ch32v10x.h"
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#include "ch32v30x.h"
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#include "debug.h"
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#include "system_ch32v10x.h"
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int main(void)
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{
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#ifndef MCU_CONFIG_H
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#define MCU_CONFIG_H
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// These were pulled out of system_ch32v10x.c
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/*
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* Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after
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* reset the HSI is used as SYSCLK source).
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* If none of the define below is enabled, the HSI is used as System clock source.
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*/
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//#define SYSCLK_FREQ_HSE HSE_VALUE
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//#define SYSCLK_FREQ_48MHz_HSE 48000000
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//#define SYSCLK_FREQ_56MHz_HSE 56000000
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#define SYSCLK_FREQ_72MHz_HSE 72000000
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//#define SYSCLK_FREQ_HSI HSI_VALUE
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//#define SYSCLK_FREQ_48MHz_HSI 48000000
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//#define SYSCLK_FREQ_56MHz_HSI 56000000
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//#define SYSCLK_FREQ_72MHz_HSI 72000000
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// These were pulled out of ch32v10x.h
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#ifndef HSE_VALUE
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#define HSE_VALUE ((uint32_t)8000000) /* Value of the External oscillator in Hz */
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#endif
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/* In the following line adjust the External High Speed oscillator (HSE) Startup Timeout value */
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#ifndef HSE_STARTUP_TIMEOUT
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#define HSE_STARTUP_TIMEOUT ((uint16_t)0x500) /* Time out for HSE start up */
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#endif
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#endif // !defined(MCU_CONFIG_H)
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@ -1,579 +0,0 @@
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/********************************** (C) COPYRIGHT *******************************
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* File Name : system_ch32v10x.c
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* Author : WCH
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* Version : V1.0.0
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* Date : 2020/04/30
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* Description : CH32V10x Device Peripheral Access Layer System Source File.
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* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
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* SPDX-License-Identifier: Apache-2.0
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*
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* modified by alexis
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*********************************************************************************/
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#include "ch32v10x.h"
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#include "mcu_config.h"
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/* Clock Definitions */
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#ifdef SYSCLK_FREQ_HSE
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uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /* System Clock Frequency (Core Clock) */
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#elif defined SYSCLK_FREQ_48MHz_HSE
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uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz_HSE; /* System Clock Frequency (Core Clock) */
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#elif defined SYSCLK_FREQ_56MHz_HSE
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uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz_HSE; /* System Clock Frequency (Core Clock) */
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#elif defined SYSCLK_FREQ_72MHz_HSE
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uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz_HSE; /* System Clock Frequency (Core Clock) */
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#elif defined SYSCLK_FREQ_48MHz_HSI
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uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz_HSI; /* System Clock Frequency (Core Clock) */
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#elif defined SYSCLK_FREQ_56MHz_HSI
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uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz_HSI; /* System Clock Frequency (Core Clock) */
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#elif defined SYSCLK_FREQ_72MHz_HSI
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uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz_HSI; /* System Clock Frequency (Core Clock) */
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#else
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uint32_t SystemCoreClock = HSI_VALUE; /* System Clock Frequency (Core Clock) */
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#endif
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__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
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/* ch32v10x_system_private_function_proto_types */
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static void SetSysClock(void);
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#ifdef SYSCLK_FREQ_HSE
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static void SetSysClockToHSE( void );
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#elif defined SYSCLK_FREQ_48MHz_HSE
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static void SetSysClockTo48_HSE( void );
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#elif defined SYSCLK_FREQ_56MHz_HSE
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static void SetSysClockTo56_HSE( void );
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#elif defined SYSCLK_FREQ_72MHz_HSE
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static void SetSysClockTo72_HSE( void );
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#elif defined SYSCLK_FREQ_48MHz_HSI
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static void SetSysClockTo48_HSI( void );
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#elif defined SYSCLK_FREQ_56MHz_HSI
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static void SetSysClockTo56_HSI( void );
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#elif defined SYSCLK_FREQ_72MHz_HSI
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static void SetSysClockTo72_HSI( void );
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#endif
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/*********************************************************************
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* @fn SystemInit
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*
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* @brief Setup the microcontroller system Initialize the Embedded Flash Interface,
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* the PLL and update the SystemCoreClock variable.
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*
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* @return none
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*/
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void SystemInit(void)
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{
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RCC->CTLR |= (uint32_t)0x00000001;
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RCC->CFGR0 &= (uint32_t)0xF8FF0000;
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RCC->CTLR &= (uint32_t)0xFEF6FFFF;
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RCC->CTLR &= (uint32_t)0xFFFBFFFF;
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RCC->CFGR0 &= (uint32_t)0xFF80FFFF;
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RCC->INTR = 0x009F0000;
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SetSysClock();
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}
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/*********************************************************************
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* @fn SystemCoreClockUpdate
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*
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* @brief Update SystemCoreClock variable according to Clock Register Values.
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*
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* @return none
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*/
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void SystemCoreClockUpdate(void)
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{
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uint32_t tmp = 0, pllmull = 0, pllsource = 0;
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tmp = RCC->CFGR0 & RCC_SWS;
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switch(tmp)
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{
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case 0x00:
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SystemCoreClock = HSI_VALUE;
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break;
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case 0x04:
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SystemCoreClock = HSE_VALUE;
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break;
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case 0x08:
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pllmull = RCC->CFGR0 & RCC_PLLMULL;
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pllsource = RCC->CFGR0 & RCC_PLLSRC;
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pllmull = (pllmull >> 18) + 2;
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if(pllsource == 0x00)
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{
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SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
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}
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else
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{
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if((RCC->CFGR0 & RCC_PLLXTPRE) != (uint32_t)RESET)
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{
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SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
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}
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else
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{
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SystemCoreClock = HSE_VALUE * pllmull;
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}
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}
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break;
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default:
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SystemCoreClock = HSI_VALUE;
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break;
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}
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tmp = AHBPrescTable[((RCC->CFGR0 & RCC_HPRE) >> 4)];
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SystemCoreClock >>= tmp;
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}
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/*********************************************************************
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* @fn SetSysClock
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*
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* @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
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*
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* @return none
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*/
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static void SetSysClock(void)
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{
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#ifdef SYSCLK_FREQ_HSE
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SetSysClockToHSE();
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#elif defined SYSCLK_FREQ_48MHz_HSE
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SetSysClockTo48_HSE();
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#elif defined SYSCLK_FREQ_56MHz_HSE
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SetSysClockTo56_HSE();
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#elif defined SYSCLK_FREQ_72MHz_HSE
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SetSysClockTo72_HSE();
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#elif defined SYSCLK_FREQ_48MHz_HSI
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SetSysClockTo48_HSI();
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#elif defined SYSCLK_FREQ_56MHz_HSI
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SetSysClockTo56_HSI();
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#elif defined SYSCLK_FREQ_72MHz_HSI
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SetSysClockTo72_HSI();
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#endif
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/* If none of the define above is enabled, the HSI is used as System clock
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* source (default after reset)
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*/
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}
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#ifdef SYSCLK_FREQ_HSE
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/*********************************************************************
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* @fn SetSysClockToHSE
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*
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* @brief Sets HSE as System clock source and configure HCLK, PCLK2 and PCLK1 prescalers.
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*
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* @return none
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*/
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static void SetSysClockToHSE(void)
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{
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__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
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RCC->CTLR |= ((uint32_t)RCC_HSEON);
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/* Wait till HSE is ready and if Time out is reached exit */
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do
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{
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HSEStatus = RCC->CTLR & RCC_HSERDY;
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StartUpCounter++;
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} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
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if((RCC->CTLR & RCC_HSERDY) != RESET)
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{
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HSEStatus = (uint32_t)0x01;
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}
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else
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{
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HSEStatus = (uint32_t)0x00;
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}
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if(HSEStatus == (uint32_t)0x01)
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{
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FLASH->ACTLR |= FLASH_ACTLR_PRFTBE;
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/* Flash 0 wait state */
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FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY);
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FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_0;
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/* HCLK = SYSCLK */
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RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
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/* PCLK2 = HCLK */
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RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
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/* PCLK1 = HCLK */
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RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1;
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/* Select HSE as system clock source */
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RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW));
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RCC->CFGR0 |= (uint32_t)RCC_SW_HSE;
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/* Wait till HSE is used as system clock source */
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while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x04)
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{
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}
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}
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else
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{
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/* If HSE fails to start-up, the application will have wrong clock
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* configuration. User can add here some code to deal with this error
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*/
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}
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}
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#elif defined SYSCLK_FREQ_48MHz_HSE
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/*********************************************************************
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* @fn SetSysClockTo48_HSE
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*
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* @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
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*
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* @return none
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*/
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static void SetSysClockTo48_HSE(void)
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{
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__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
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RCC->CTLR |= ((uint32_t)RCC_HSEON);
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/* Wait till HSE is ready and if Time out is reached exit */
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do
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{
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HSEStatus = RCC->CTLR & RCC_HSERDY;
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StartUpCounter++;
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} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
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if((RCC->CTLR & RCC_HSERDY) != RESET)
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{
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HSEStatus = (uint32_t)0x01;
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}
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else
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{
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HSEStatus = (uint32_t)0x00;
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}
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if(HSEStatus == (uint32_t)0x01)
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{
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/* Enable Prefetch Buffer */
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FLASH->ACTLR |= FLASH_ACTLR_PRFTBE;
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/* Flash 1 wait state */
|
||||
FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY);
|
||||
FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_1;
|
||||
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
/* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLMULL6);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/*
|
||||
* If HSE fails to start-up, the application will have wrong clock
|
||||
* configuration. User can add here some code to deal with this error
|
||||
*/
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined SYSCLK_FREQ_56MHz_HSE
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo56_HSE
|
||||
*
|
||||
* @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo56_HSE(void)
|
||||
{
|
||||
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
||||
|
||||
RCC->CTLR |= ((uint32_t)RCC_HSEON);
|
||||
|
||||
/* Wait till HSE is ready and if Time out is reached exit */
|
||||
do
|
||||
{
|
||||
HSEStatus = RCC->CTLR & RCC_HSERDY;
|
||||
StartUpCounter++;
|
||||
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
||||
|
||||
if((RCC->CTLR & RCC_HSERDY) != RESET)
|
||||
{
|
||||
HSEStatus = (uint32_t)0x01;
|
||||
}
|
||||
else
|
||||
{
|
||||
HSEStatus = (uint32_t)0x00;
|
||||
}
|
||||
|
||||
if(HSEStatus == (uint32_t)0x01)
|
||||
{
|
||||
/* Enable Prefetch Buffer */
|
||||
FLASH->ACTLR |= FLASH_ACTLR_PRFTBE;
|
||||
|
||||
/* Flash 2 wait state */
|
||||
FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY);
|
||||
FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_2;
|
||||
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
/* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLMULL7);
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/*
|
||||
* If HSE fails to start-up, the application will have wrong clock
|
||||
* configuration. User can add here some code to deal with this error
|
||||
*/
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined SYSCLK_FREQ_72MHz_HSE
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo72_HSE
|
||||
*
|
||||
* @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo72_HSE(void)
|
||||
{
|
||||
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
||||
|
||||
RCC->CTLR |= ((uint32_t)RCC_HSEON);
|
||||
|
||||
/* Wait till HSE is ready and if Time out is reached exit */
|
||||
do
|
||||
{
|
||||
HSEStatus = RCC->CTLR & RCC_HSERDY;
|
||||
StartUpCounter++;
|
||||
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
||||
|
||||
if((RCC->CTLR & RCC_HSERDY) != RESET)
|
||||
{
|
||||
HSEStatus = (uint32_t)0x01;
|
||||
}
|
||||
else
|
||||
{
|
||||
HSEStatus = (uint32_t)0x00;
|
||||
}
|
||||
|
||||
if(HSEStatus == (uint32_t)0x01)
|
||||
{
|
||||
/* Enable Prefetch Buffer */
|
||||
FLASH->ACTLR |= FLASH_ACTLR_PRFTBE;
|
||||
|
||||
/* Flash 2 wait state */
|
||||
FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY);
|
||||
FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_2;
|
||||
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
/* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE |
|
||||
RCC_PLLMULL));
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLMULL9);
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/*
|
||||
* If HSE fails to start-up, the application will have wrong clock
|
||||
* configuration. User can add here some code to deal with this error
|
||||
*/
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined SYSCLK_FREQ_48MHz_HSI
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo48_HSI
|
||||
*
|
||||
* @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo48_HSI(void)
|
||||
{
|
||||
EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
|
||||
|
||||
/* Enable Prefetch Buffer */
|
||||
FLASH->ACTLR |= FLASH_ACTLR_PRFTBE;
|
||||
|
||||
/* Flash 1 wait state */
|
||||
FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY);
|
||||
FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_1;
|
||||
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
/* PLL configuration: PLLCLK = HSI * 6 = 48 MHz */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL6);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined SYSCLK_FREQ_56MHz_HSI
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo56_HSI
|
||||
*
|
||||
* @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo56_HSI(void)
|
||||
{
|
||||
EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
|
||||
|
||||
/* Enable Prefetch Buffer */
|
||||
FLASH->ACTLR |= FLASH_ACTLR_PRFTBE;
|
||||
|
||||
/* Flash 1 wait state */
|
||||
FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY);
|
||||
FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_1;
|
||||
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
/* PLL configuration: PLLCLK = HSI * 7 = 56 MHz */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL7);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined SYSCLK_FREQ_72MHz_HSI
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo72_HSI
|
||||
*
|
||||
* @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo72_HSI(void)
|
||||
{
|
||||
EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
|
||||
|
||||
/* Enable Prefetch Buffer */
|
||||
FLASH->ACTLR |= FLASH_ACTLR_PRFTBE;
|
||||
|
||||
/* Flash 1 wait state */
|
||||
FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY);
|
||||
FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_1;
|
||||
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
/* PLL configuration: PLLCLK = HSI * 9 = 72 MHz */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL9);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
#endif
|
|
@ -1,27 +0,0 @@
|
|||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : system_ch32v10x.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2020/04/30
|
||||
* Description : CH32V10x Device Peripheral Access Layer System Header File.
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*******************************************************************************/
|
||||
#ifndef __SYSTEM_CH32V10x_H
|
||||
#define __SYSTEM_CH32V10x_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */
|
||||
|
||||
/* System_Exported_Functions */
|
||||
extern void SystemInit(void);
|
||||
extern void SystemCoreClockUpdate(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__CH32V10x_SYSTEM_H */
|
|
@ -1 +0,0 @@
|
|||
Subproject commit 5f727a548b888f28669ab063b69b8d6f07298695
|
|
@ -0,0 +1 @@
|
|||
Subproject commit 6c6fa38d8912e46e56ffab728ab748b45284314f
|
|
@ -0,0 +1 @@
|
|||
Subproject commit 8d8a376858f6e27a6a229762f1406dc9bf85a555
|
Loading…
Reference in New Issue