||7 months ago|
|PLDs||7 months ago|
|gen||7 months ago|
|icm68m||7 months ago|
|icm68m-evk||7 months ago|
|misc||7 months ago|
|.gitignore||7 months ago|
|README.md||7 months ago|
This project is IN DEVELOPMENT! All promises made below are lies.
ICM68M (instrument control module, 68k, mini) is a reduced/budget version of the ICM68K. It is an embeddable M68000 computer for controlling small, simple instruments and similar electronic devices, intended for use with the A6 operating system.
- MC68EC000 processor running at 16 MHz on an 8-bit bus
- 512kByte onboard flash, externally expandable
- 512kByte onboard RAM, externally expandable
- Dual UART, up to 115200 baud
- Eight fast general-purpose outputs
- Eight fast general-purpose inputs, two with interrupt-on-change
Omissions from the ICM68K:
- No memory protection unit
- No SPI transceiver
- No real-time clock
- No micro-SD slot
- No full-featured GPIO with output mode control
- No beeper
- Less memory
A bootloader is provided in flash to allow loading firmware over the UART; this bootloader takes up (TODO: TBD) 4kB of the onboard flash. The bootloader can write to offboard flash as well as the onboard.
Necessary bus connections
Especially when using the onboard bootloader, a few connections must be made externally if not using certain expansion features:
- nCS_FLASH1 should connect to nBERR through a diode (anode to nBERR) if not expanding flash, unless the application board contains a bus timeout generator.
Direct support is provided for doubling the onboard flash and RAM with one more identical chip of each on the application board — all constrol signals are provided on the mezzanine connector. The remaining 13 megabytes of address space may also be extended with external address decoders as desired.
Doubling the memory
The ICM68M is directly compatible with the SST39SF040 flash chip and the IS61C5128AS-25QLI static RAM, each with a 512kB capacity. To add these, wire them to the system bus directly (A18-A0 to A18-A0, D7-D0 to D7-D0), and connect nWE to sysbus RnW, nOE to sysmus MEMnOE, and nCS to one of nCS_FLASH1 and nCS_RAM1. Equivalent parts may be used but must be 5V compatible.
Extending the memory further
If large memory capacity is desired, up to 13 MB may be added to the system bus region of address space. Connections are made as follows:
- Address decode logic should sense address bits. The design of this decoder is up to the implementer. Note that the system bus address range spans from 100000 through DFFFFF. The onboard address decoder provides a nCS_SYSBUS output whenever the address is within this range, so an implementation may take advantage of this to simplify decode.
- The system bus RnW signal maps to the nWE input of most memory devices.
- The additional output MEMnOE from the onboard address decoder may be used for the nOE input; this is simply the inverse of RnW (WnR).
- The nCS input of most memory devices should be generated by the address decode logic. It should be gated by either nCS_SYSBUS if decoding partial addresses or (nAS | nDS) if decoding the entire address (ensure there are no conflicts with onboard devices!). The 74HCT138 decoder can provide this with no additional logic.
- If connected directly to the bus, memory devices must tolerate 5V and must accept inputs down to 2V as a valid "high" (TTL levels). Note that above about 512 kB this becomes prohibitively expensive to do directly; a level-clamping bus switch or translating buffers may be used to interface cheap PSRAM devices. The bus speed is relatively fast due to the high-speed 68EC000 so the bus switch variant is generally preferable due to low propagation delay.
- You must provide the nDTACK signal for any devices on the system bus. This may simply be equal to the enable signal for your address decoder (you can just feed nCS_SYSBUS into BUS_DTACK if you like). If using memory devices with lower operating speed you may choose to delay this signal with a flip-flop to give extra time for accesses.