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SOM board before starting autoroute

trunk
alexis 2021-09-21 20:27:11 -06:00
parent 15913087ba
commit a9d73650dd
20 changed files with 141566 additions and 0 deletions
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7
documentation/0.6_BARCODES.txt Normal file
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Content-Type: text/x-zim-wiki
Wiki-Format: zim 0.6
Creation-Date: 2021-08-31T09:33:05-06:00
====== 0.6 BARCODES ======
Created Tuesday 31 August 2021

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parts/A04-som/A04-som.bin Normal file
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parts/A04-som/A04-som.dsn Normal file
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parts/A04-som/A04-som.kicad_dru Normal file
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(version 1)
#(rule "InnerLayerTrackSpace"
# (condition "A.existsOnLayer('In*.Cu')")
# (constraint track_width (min 5mil))
# (constraint clearance (min 5mil)))
(rule "ViaToTrack"
(condition "A.Type == 'via' && B.Type == 'track'")
(constraint hole_clearance (min 0.127mm)))
(rule "ViaToVia_SameNet"
(condition "A.Type == 'via' && A.Net == B.Net")
(constraint hole_to_hole (min 0.127mm))
(constraint hole_clearance (min 0.127mm)))
(rule "PadToEdge"
(condition "A.Type == 'pad'")
(constraint edge_clearance (min 1mm)))
(rule "SilkZoneOverPads"
(condition "A.Type == 'zone' && A.existsOnLayer('*.Silkscreen') && B.existsOnLayer('*.Mask')")
(constraint silk_clearance (min -0.1mm)))

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parts/A04-som/A04-som.kicad_pcb Normal file
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parts/A04-som/A04-som.kicad_prl Normal file
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{
"board": {
"active_layer": 0,
"active_layer_preset": "",
"auto_track_width": false,
"hidden_nets": [],
"high_contrast_mode": 0,
"net_color_mode": 1,
"opacity": {
"pads": 1.0,
"tracks": 1.0,
"vias": 1.0,
"zones": 0.6
},
"ratsnest_display_mode": 0,
"selection_filter": {
"dimensions": true,
"footprints": true,
"graphics": true,
"keepouts": true,
"lockedItems": true,
"otherItems": true,
"pads": true,
"text": true,
"tracks": true,
"vias": true,
"zones": true
},
"visible_items": [
0,
1,
2,
3,
4,
5,
6,
8,
9,
10,
11,
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13,
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],
"visible_layers": "003f3dc_8000001f",
"zone_display_mode": 1
},
"meta": {
"filename": "A04-som.kicad_prl",
"version": 3
},
"project": {
"files": [
{
"name": "A04-som.kicad_pcb",
"open": false,
"window": {
"display": 0,
"maximized": true,
"pos_x": 0,
"pos_y": 0,
"size_x": 1120,
"size_y": 620
}
},
{
"name": "A04-som.kicad_sch",
"open": false,
"window": {
"display": 0,
"maximized": true,
"pos_x": 0,
"pos_y": 0,
"size_x": 1270,
"size_y": 686
}
}
]
}
}

567
parts/A04-som/A04-som.kicad_pro Normal file
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{
"board": {
"design_settings": {
"defaults": {
"board_outline_line_width": 0.09999999999999999,
"copper_line_width": 0.19999999999999998,
"copper_text_italic": false,
"copper_text_size_h": 1.5,
"copper_text_size_v": 1.5,
"copper_text_thickness": 0.3,
"copper_text_upright": false,
"courtyard_line_width": 0.049999999999999996,
"dimension_precision": 4,
"dimension_units": 3,
"dimensions": {
"arrow_length": 1270000,
"extension_offset": 500000,
"keep_text_aligned": true,
"suppress_zeroes": false,
"text_position": 0,
"units_format": 1
},
"fab_line_width": 0.09999999999999999,
"fab_text_italic": false,
"fab_text_size_h": 0.5,
"fab_text_size_v": 0.5,
"fab_text_thickness": 0.09999999999999999,
"fab_text_upright": false,
"other_line_width": 0.15,
"other_text_italic": false,
"other_text_size_h": 1.0,
"other_text_size_v": 1.0,
"other_text_thickness": 0.15,
"other_text_upright": false,
"pads": {
"drill": 1.835,
"height": 3.0,
"width": 3.0
},
"silk_line_width": 0.19999999999999998,
"silk_text_italic": false,
"silk_text_size_h": 0.7999999999999999,
"silk_text_size_v": 0.7999999999999999,
"silk_text_thickness": 0.19999999999999998,
"silk_text_upright": false,
"zones": {
"45_degree_only": false,
"min_clearance": 0.508
}
},
"diff_pair_dimensions": [
{
"gap": 0.0,
"via_gap": 0.0,
"width": 0.0
}
],
"drc_exclusions": [],
"meta": {
"version": 2
},
"rule_severities": {
"annular_width": "error",
"clearance": "error",
"copper_edge_clearance": "error",
"courtyards_overlap": "error",
"diff_pair_gap_out_of_range": "error",
"diff_pair_uncoupled_length_too_long": "error",
"drill_out_of_range": "error",
"duplicate_footprints": "warning",
"extra_footprint": "warning",
"hole_clearance": "error",
"hole_near_hole": "error",
"invalid_outline": "error",
"item_on_disabled_layer": "error",
"items_not_allowed": "error",
"length_out_of_range": "error",
"malformed_courtyard": "error",
"microvia_drill_out_of_range": "error",
"missing_courtyard": "ignore",
"missing_footprint": "warning",
"net_conflict": "warning",
"npth_inside_courtyard": "ignore",
"padstack": "error",
"pth_inside_courtyard": "ignore",
"shorting_items": "error",
"silk_over_copper": "warning",
"silk_overlap": "warning",
"skew_out_of_range": "error",
"too_many_vias": "error",
"track_dangling": "warning",
"track_width": "error",
"tracks_crossing": "error",
"unconnected_items": "error",
"unresolved_variable": "error",
"via_dangling": "warning",
"zone_has_empty_net": "error",
"zones_intersect": "error"
},
"rules": {
"allow_blind_buried_vias": false,
"allow_microvias": false,
"max_error": 0.005,
"min_clearance": 0.08889999999999999,
"min_copper_edge_clearance": 0.19999999999999998,
"min_hole_clearance": 0.127,
"min_hole_to_hole": 0.0,
"min_microvia_diameter": 0.19999999999999998,
"min_microvia_drill": 0.09999999999999999,
"min_silk_clearance": 0.15,
"min_through_hole_diameter": 0.19999999999999998,
"min_track_width": 0.08889999999999999,
"min_via_annular_width": 0.09999999999999999,
"min_via_diameter": 0.39999999999999997,
"solder_mask_clearance": 0.0,
"solder_mask_min_width": 0.0,
"use_height_for_length_calcs": true
},
"track_widths": [
0.0,
0.127,
0.14,
0.25,
0.3,
0.5,
0.8,
1.0,
1.25,
1.5
],
"via_dimensions": [
{
"diameter": 0.0,
"drill": 0.0
},
{
"diameter": 0.4,
"drill": 0.2
},
{
"diameter": 0.6,
"drill": 0.3
},
{
"diameter": 0.8,
"drill": 0.4
}
],
"zones_allow_external_fillets": true,
"zones_use_no_outline": true
},
"layer_presets": []
},
"boards": [],
"cvpcb": {
"equivalence_files": []
},
"erc": {
"erc_exclusions": [],
"meta": {
"version": 0
},
"pin_map": [
[
0,
0,
0,
0,
0,
0,
1,
0,
0,
0,
0,
2
],
[
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0,
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2,
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],
[
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],
[
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],
[
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],
[
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],
[
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],
[
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],
[
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],
[
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],
[
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2
],
[
2,
2,
2,
2,
2,
2,
2,
2,
2,
2,
2,
2
]
],
"rule_severities": {
"bus_definition_conflict": "error",
"bus_entry_needed": "error",
"bus_label_syntax": "error",
"bus_to_bus_conflict": "error",
"bus_to_net_conflict": "error",
"different_unit_footprint": "error",
"different_unit_net": "error",
"duplicate_reference": "error",
"duplicate_sheet_names": "error",
"extra_units": "error",
"global_label_dangling": "warning",
"hier_label_mismatch": "error",
"label_dangling": "error",
"lib_symbol_issues": "warning",
"multiple_net_names": "warning",
"net_not_bus_member": "warning",
"no_connect_connected": "warning",
"no_connect_dangling": "warning",
"pin_not_connected": "error",
"pin_not_driven": "error",
"pin_to_pin": "error",
"power_pin_not_driven": "error",
"similar_labels": "warning",
"unannotated": "error",
"unit_value_mismatch": "error",
"unresolved_variable": "error",
"wire_dangling": "error"
}
},
"libraries": {
"pinned_footprint_libs": [],
"pinned_symbol_libs": []
},
"meta": {
"filename": "A04-som.kicad_pro",
"version": 1
},
"net_settings": {
"classes": [
{
"bus_width": 12.0,
"clearance": 0.127,
"diff_pair_gap": 0.0,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.0,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "Default",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.127,
"via_diameter": 0.4,
"via_drill": 0.2,
"wire_width": 6.0
},
{
"bus_width": 12.0,
"clearance": 0.127,
"diff_pair_gap": 0.1397,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.082804,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "110ohmDiff",
"nets": [
"/CPU/SDRAM.CLK+",
"/CPU/SDRAM.CLK-",
"/ERX+",
"/ERX-",
"/ETX+",
"/ETX-",
"/FPGA Bus/PSRAM.CK+",
"/FPGA Bus/PSRAM.CK-"
],
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.120142,
"via_diameter": 0.4,
"via_drill": 0.2,
"wire_width": 6.0
},
{
"bus_width": 12.0,
"clearance": 0.127,
"diff_pair_gap": 0.0,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.0,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "55ohm",
"nets": [
"/CPU/SDRAM.CKE",
"/CPU/SDRAM.VREF",
"/CPU/SDRAM.~{CAS}",
"/CPU/SDRAM.~{CS}",
"/CPU/SDRAM.~{RAS}",
"/CPU/SDRAM.~{WE}",
"/FPGA Bus/PSRAM.RWDS",
"/FPGA Bus/PSRAM.~{CS}",
"/FPGA Bus/PSRAM.~{RESET}"
],
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.120142,
"via_diameter": 0.4,
"via_drill": 0.2,
"wire_width": 6.0
},
{
"bus_width": 12.0,
"clearance": 0.127,
"diff_pair_gap": 0.127,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.131318,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "90ohmDiff",
"nets": [
"/CPU/USB1.D+",
"/CPU/USB1.D-",
"/CPU/USB2.D+",
"/CPU/USB2.D-",
"/CPU/USB3.D+",
"/CPU/USB3.D-"
],
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.131318,
"via_diameter": 0.4,
"via_drill": 0.2,
"wire_width": 6.0
}
],
"meta": {
"version": 2
},
"net_colors": null
},
"pcbnew": {
"last_paths": {
"gencad": "",
"idf": "",
"netlist": "",
"specctra_dsn": "A04-som.dsn",
"step": "",
"vrml": ""
},
"page_layout_descr_file": "${ALEXISVL}/basic.kicad_wks"
},
"schematic": {
"annotate_start_num": 0,
"drawing": {
"default_bus_thickness": 12.0,
"default_junction_size": 40.0,
"default_line_thickness": 6.0,
"default_text_size": 50.0,
"default_wire_thickness": 6.0,
"field_names": [],
"intersheets_ref_own_page": false,
"intersheets_ref_prefix": "",
"intersheets_ref_short": false,
"intersheets_ref_show": true,
"intersheets_ref_suffix": "",
"junction_size_choice": 3,
"label_size_ratio": 0.375,
"pin_symbol_size": 25.0,
"text_offset_ratio": 0.15
},
"legacy_lib_dir": "",
"legacy_lib_list": [],
"meta": {
"version": 1
},
"net_format_name": "",
"ngspice": {
"fix_include_paths": true,
"fix_passive_vals": false,
"meta": {
"version": 0
},
"model_mode": 0,
"workbook_filename": ""
},
"page_layout_descr_file": "${ALEXISVL}/basic.kicad_wks",
"plot_directory": "",
"spice_adjust_passive_values": false,
"spice_external_command": "spice \"%I\"",
"subpart_first_id": 65,
"subpart_id_separator": 0
},
"sheets": [
[
"6cbca710-7cbe-4156-8860-98558c1f844f",
""
],
[
"50481398-57b8-4c2a-a52f-a986422e441c",
"Memory"
],
[
"ba5ac381-81bf-4095-97c6-3708f944b8c6",
"FPGA Bus"
],
[
"dee1ad2d-f0e5-466a-b8b5-333bb6b6994c",
"CPU"
],
[
"b7250151-822e-4c37-bf74-006ce27e578c",
"Power Distribution"
],
[
"9695630f-9869-470c-87dd-8e05130a8c97",
"Power Supply"
],
[
"ea1cdcc5-6eb7-46f4-acdc-cf1d2260b5fe",
"Clock"
],
[
"06072620-3023-4108-af1a-b04a14533470",
"Interfaces"
],
[
"4076e994-9743-4665-8e0d-cb96b3922fbd",
"FPGA_and_NV"
]
],
"text_variables": {}
}

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parts/A04-som/A04-som.kicad_sch Normal file
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parts/A04-som/Clock.kicad_sch Normal file
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parts/A04-som/FPGABus.kicad_sch Normal file
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parts/A04-som/FPGA_and_NV.kicad_sch Normal file
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parts/A04-som/PowerDistribution.kicad_sch Normal file
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parts/A04-som/PowerSeq.kicad_sch Normal file
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(kicad_sch (version 20210621) (generator eeschema)
(uuid 28807248-0173-4167-bc14-1987ccc532cb)
(paper "A4")
(lib_symbols
)
)

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parts/A04-som/PowerSupply.kicad_sch Normal file
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parts/A04-som/mpu.kicad_sym Normal file
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parts/A04-som/supervisor-fw/supervisor.c Normal file
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// /opt/microchip/xc8/v2.32/bin/xc8-cc -mcpu=attiny806 -O2 supervisor.c
#define F_CPU 1000000
#include <avr/io.h>
#include <util/delay.h>
#include <stdbool.h>
FUSES = {
.WDTCFG = 0,
.BODCFG = BOD_LVL_BODLEVEL2_gc, // 2.6V
.OSCCFG = FREQSEL_16MHZ_gc,
.SYSCFG0 = CRCSRC_NOCRC_gc | RSTPINCFG_UPDI_gc,
.SYSCFG1 = SUT_4MS_gc,
.APPEND = 0,
.BOOTEND = 0,
};
#define PORT_PWREN PORTA
#define PIN_PWREN_bp 7u
#define PORT_EN_MOST PORTB
#define PIN_EN_MOST_bp 0u
#define PORT_EN_VCORE PORTB
#define PIN_EN_VCORE_bp 1u
#define PORT_CPU_nRST PORTB
#define PIN_CPU_nRST_bp 3u
#define PORT_CPU_nSHDN PORTB
#define PIN_CPU_nSHDN_bp 4u
#define PORT_nEN_FPGA_VCCAUX PORTB
#define PIN_nEN_FPGA_VCCAUX_bp 5u
#define PORT_nSEL_5V PORTC
#define PIN_nSEL_5V_bp 0u
#define PIN_VIN_AIN 1
#define PIN_5V0_AIN 2
#define PIN_3V3_AIN 3
#define PIN_2V5_AIN 4
#define PIN_1V8_AIN 5
#define PIN_1V2_AIN 6
#define PORT_ANALOG PORTA
#define PINS_ANALOG_gm 0x7Eu
static void _check_and_drive_sel5v(void);
static void _wait_pwrgd_1v2(void);
static void _wait_pwrgd(void);
static void _do_startup(void);
static void _do_shutdown(void);
int main(void)
{
_PROTECTED_WRITE(CLKCTRL.MCLKCTRLA, CLKCTRL_CLKSEL_OSC20M_gc);
_PROTECTED_WRITE(CLKCTRL.MCLKCTRLB, CLKCTRL_PDIV_16X_gc | CLKCTRL_PEN_bm);
PORT_PWREN.DIR &= ~(1u << PIN_PWREN_bp);
PORT_EN_MOST.OUT &= ~(1u << PIN_EN_MOST_bp); // init 0
PORT_EN_MOST.DIR |= (1u << PIN_EN_MOST_bp);
PORT_EN_VCORE.OUT &= ~(1u << PIN_EN_VCORE_bp); // init 0
PORT_EN_VCORE.DIR |= (1u << PIN_EN_VCORE_bp);
PORT_CPU_nRST.OUT &= ~(1u << PIN_CPU_nRST_bp); // init 0
PORT_CPU_nRST.DIR |= (1u << PIN_CPU_nRST_bp);
PORT_CPU_nSHDN.OUT &= ~(1u << PIN_CPU_nSHDN_bp); // init 0
PORT_CPU_nSHDN.DIR |= (1u << PIN_CPU_nSHDN_bp);
PORT_nEN_FPGA_VCCAUX.OUT |= (1u << PIN_nEN_FPGA_VCCAUX_bp); // init 1
PORT_nEN_FPGA_VCCAUX.DIR |= (1u << PIN_nEN_FPGA_VCCAUX_bp); // init 1
// Shut off the input buffers on analog inputs
uint8_t volatile * pinctrl = &PORT_ANALOG.PIN0CTRL;
uint8_t pin_bit = 1;
for (uint8_t i = 0; i < 8; i++, pin_bit <<= 1, pinctrl++)
{
if (PINS_ANALOG_gm & pin_bit)
{
*pinctrl = PORT_ISC_INPUT_DISABLE_gc;
}
}
bool state = false;
for (;;)
{
bool const pwren = (PORT_PWREN.IN & (1u << PIN_PWREN_bp));
if (pwren && !state)
{
state = true;
_do_startup();
}
else if (!pwren && state)
{
state = false;
_do_shutdown();
}
}
}
static void _do_startup(void)
{
_delay_ms(1);
_check_and_drive_sel5v();
PORT_nEN_FPGA_VCCAUX.OUT |= 1u << PIN_nEN_FPGA_VCCAUX_bp;
PORT_EN_VCORE.OUT |= (1u << PIN_EN_VCORE_bp);
_wait_pwrgd_1v2();
_delay_ms(1);
PORT_EN_MOST.OUT |= (1u << PIN_EN_MOST_bp);
_wait_pwrgd();
_delay_ms(1);
PORT_nEN_FPGA_VCCAUX.OUT &= ~(1u << PIN_nEN_FPGA_VCCAUX_bp);
PORT_CPU_nSHDN.DIR &= ~(1u << PIN_CPU_nSHDN_bp);
PORT_CPU_nRST.DIR &= ~(1u << PIN_CPU_nRST_bp);
}
static void _do_shutdown(void)
{
PORT_CPU_nSHDN.DIR |= (1u << PIN_CPU_nSHDN_bp);
_delay_ms(250);
PORT_CPU_nRST.DIR |= (1u << PIN_CPU_nRST_bp);
_delay_ms(1);
PORT_EN_MOST.OUT &= ~(1u << PIN_EN_MOST_bp);
PORT_EN_VCORE.OUT &= ~(1u << PIN_EN_VCORE_bp);
}
static void _check_and_drive_sel5v(void)
{
}
static void _wait_pwrgd_1v2(void)
{
}
static void _wait_pwrgd(void)
{
}

3
parts/A04-som/sym-lib-table Normal file
View File

@ -0,0 +1,3 @@
(sym_lib_table
(lib (name "mpu")(type "KiCad")(uri "${KIPRJMOD}/mpu.kicad_sym")(options "")(descr ""))
)