Write a little of the TOO
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# TIMDAC Theory of Operation
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TIMDAC is _not_ a PWM DAC, where a waveform is generated whose average value
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equals the desired output, and then filtered all the way down to DC. To get
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precision-DAC levels of resolution from this, a PWM DAC must be filtered so
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steeply that its settling time becomes enormous (around 5ms for 1 LSB ripple
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at 15 bits, 50ms for 0.1LSB ripple, and so on), and this settling time also
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significantly limits the ability to scan a large number of channels.
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Instead, TIMDAC uses an integrating sample-and-hold topology. A single pulse
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is integrated, producing a ramp from 0 up to the product of the pulse width
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and the reference slope. At the end of the pulse, the final value is sampled
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and held in an output capacitor. TIMDAC can update in as little as 1.3ms, with
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an "ideally zero" ripple limited only by analog switch performance and layout
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quality.
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## Hardware
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TODO: reference design here
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### Reference chopper
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### Integrator and ramp inverter
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### Tuning comparator
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### Polarity switch and output multiplexer
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### Sample-and-hold amplifiers
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## Firmware
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### Layer 1: low-level DAC driver
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TODO: state diagram here
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### Layer 2: tuning driver
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TODO: state diagram here
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### Layer 3: scan driver
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TODO: state diagram here
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