Write a little of the TOO

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alexis 2023-01-02 16:29:50 -07:00
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# TIMDAC Theory of Operation
TIMDAC is _not_ a PWM DAC, where a waveform is generated whose average value
equals the desired output, and then filtered all the way down to DC. To get
precision-DAC levels of resolution from this, a PWM DAC must be filtered so
steeply that its settling time becomes enormous (around 5ms for 1 LSB ripple
at 15 bits, 50ms for 0.1LSB ripple, and so on), and this settling time also
significantly limits the ability to scan a large number of channels.
Instead, TIMDAC uses an integrating sample-and-hold topology. A single pulse
is integrated, producing a ramp from 0 up to the product of the pulse width
and the reference slope. At the end of the pulse, the final value is sampled
and held in an output capacitor. TIMDAC can update in as little as 1.3ms, with
an "ideally zero" ripple limited only by analog switch performance and layout
quality.
## Hardware
TODO: reference design here
### Reference chopper
### Integrator and ramp inverter
### Tuning comparator
### Polarity switch and output multiplexer
### Sample-and-hold amplifiers
## Firmware
### Layer 1: low-level DAC driver
TODO: state diagram here
### Layer 2: tuning driver
TODO: state diagram here
### Layer 3: scan driver
TODO: state diagram here